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IDT79R3081E - RISController with FPA

Download the IDT79R3081E datasheet PDF. This datasheet also covers the IDT variant, as both devices belong to the same riscontroller with fpa family and are provided as variant models within a single manufacturer datasheet.

General Description

of this processor.

The R3051, which incorporates 4kB of instruction cache and 2kB of data cache, but omits the TLB, and instead uses a simpler virtual to physical address mapping.

The R3081E, which incorporates a 16kB instruction cache, a 4kB data cache, and full function memory

Key Features

  • Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs.
  • High level of integration minimizes system cost.
  • R3000A Compatible CPU.
  • R3010A Compatible Floating Point Accelerator.
  • Optional R3000A compatible MMU.
  • Large Instruction Cache.
  • Large Data Cache.
  • Read/Write Buffers.
  • 43VUPS at 50MHz.
  • 13MFlops.
  • Flexible bus interface allows simple, low cost designs.
  • Optional 1x or.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT-79R3.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT79R3081E
Manufacturer Integrated Device
File Size 294.34 KB
Description RISController with FPA
Datasheet download datasheet IDT79R3081E Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IDT79R3081 RISController MILITARY AND COMMERCIAL TEMPERATURE RANGES Integrated Device Technology, Inc. IDT79R3081 RISController™ with FPA IDT 79R3081™ , 79R3081E IDT 79RV3081, 79RV3081E FEATURES • Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs • High level of integration minimizes system cost — R3000A Compatible CPU — R3010A Compatible Floating Point Accelerator — Optional R3000A compatible MMU — Large Instruction Cache — Large Data Cache — Read/Write Buffers • 43VUPS at 50MHz — 13MFlops • Flexible bus interface allows simple, low cost designs • Optional 1x or 2x clock input • 20 through 50MHz operation • "V" version operates at 3.